HD6432633 Datasheet, PDF (946/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

21.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 21-1 shows the address and initial value of
SYSCR.
Table 21-1 RAM Register
Name
Abbreviation R/W
System control register
SYSCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'01
Address*
H'FDE5
21.2 Register Descriptions
21.2.1 System Control Register (SYSCR)
Bit
:
Initial value :
R/W
:
7
MACS
0
R/W
6
5
4
3
2
1
0
— INTM1 INTM0 NMIEG MRESE — RAME
0
0
0
0
0
0
1
—
R/W R/W R/W R/W
—
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Note: When the DTC* is used, the RAME bit must not be cleared to 0.
* The DTC function is not available in the H8S/2695.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
892