HD6432633 Datasheet, PDF (262/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.5.5 DRAM Interface Pins
Table 7-7 shows the pins used for the DRAM interface, and their functions.
Table 7-7 DRAM Interface Pin Configuration
In DRAM
Pin
Mode
Name
Direction Function
HWR
WE
Write enable
Output
Write enable when accessing
DRAM space in 2 CAS mode
LCAS
LCAS
Lower column address Output
strobe
Lower column address strobe signal
when accessing 16-bit DRAM space
CS2
RAS2
Row address strobe 2 Output
Row address strobe when area 2
set as DRAM space
CS3
RAS3
Row address strobe 3 Output
Row address strobe when area 3
set as DRAM space
CS4
RAS4
Row address strobe 4 Output
Row address strobe when area 4
set as DRAM space
CS5
RAS5
Row address strobe 5 Output
Row address strobe when area 5
set as DRAM space
CAS
UCAS
Upper column address Output
strobe
Upper column address strobe when
accessing DRAM space
WAIT
WAIT
Wait
Input
Wait request signal
A12 to A0 A12 to A0 Address pin
Output
Multiplexed output of row address
and column address
D15 to D0 D15 to D0 Data pin
Input/output Data input/output pin
OE
OE*
Output enable pin
Output
Output enable signal when
accessing DRAM space in read
mode
Note: * Valid when OES bit set to 1.
7.5.6 Basic Timing
Figure 7-15 shows the basic access timing for DRAM space. There are four basic DRAM timing
states. In contrast to the standard bus interface, the corresponding ASTCR bit only controls the
enabling/disabling of wait insertion and has no effect on the number of access states. When the
corresponding ASTCR bit is cleared to 0, no wait states can be inserted in the DRAM access
cycle.
The four basic timing states are as follows: T_P (precharge cycle) 1 state, T_r (row address output
cycle) 1 state, T_c1 and T_c2 (column address output cycle) two states.
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