HD6432633 Datasheet, PDF (266/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

(2) Insertion of Pin Waits
When the WAITE bit of BCRH is set to 1, wait input via the WAIT pin is valid regardless of the
ASTCR AST bit. In this state, a program wait is inserted when the DRAM space is accessed. If the
WAIT pin level is Low at the fall in ø in the final T_c1 or T_w state, a further T_w is inserted. If the
level of the WAIT pin is kept Low, T_w is inserted until the level of the WAIT pin changes to High.
When wait states are inserted via the WAIT pin, the CAS when writing is output after the T_w state.
Figure 7-18 shows example timing for the insertion of wait states via the WAIT pin.
Program
waits
WAIT pin wait states
T_p
T_r
T_c1
T_w
T_w
T_c2
ø
Address bus
AS
CSn (RAS)
CAS, LCAS
Read
RD
RCTS= 0
RCTS= 1
Data bus
Read data
CAS, LCAS
Write _{HWR (WE)}
Data bus
Write data
Note: ↓ shows timing for /WAIT pin sampling.
n= 2 to 5
Figure 7-18 Example Timing for Insertion of Wait States via WAIT Pin
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