HD6432633 Datasheet, PDF (725/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
15.1 Overview
The H8S/2633 Series has a two channel inbuilt watchdog timer, (WDT0/WDT1). The WDT
outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the
timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal
reset signal for the H8S/2633 Series.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
15.1.1 Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
• WDTOVF output when in watchdog timer mode
If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether the LSI
is internally reset or an NMI interrupt is generated at the same time.
This internal reset is effected by either a power-on reset or a manual reset.
• Interrupt generation when in interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt.
• WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be
selected
The maximum interval of the WDT is given as a system clock cycle × 131072 × 256.
A subclock may be selected for the input counter of WDT1*.
Where a subclock is selected, the maximum interval is given as a subclock cycle × 256 × 256.
• Selected clock can be output from the BUZZ* output pin (WDT1)*
Note: * This function is not available in the H8S/2695.
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