HD6432633 Datasheet, PDF (592/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 3 Bit 2 Bit 1 Bit 0
Channel IOC3 IOC2 IOC1 IOC0 Description
3
0 0 0 0 TGR3C is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register*¹
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1 0 0 0 TGR3C is Capture input Input capture at rising edge
1
input
source is
capture TIOCC3 pin
Input capture at falling edge
1
*
register*¹
Input capture at both edges
1
*
*
Capture input Input capture at TCNT4
source is channel count-up/count-down
4/count clock
*: Don’t care
Note: *1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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