HD6432633 Datasheet, PDF (19/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Section
Page
Item
Description
18.3.9 Noise Canceler 
Figure 18-14 Flowchart for
Master Transmit Mode
(Example)
Deleted
Figure 18-15 Flowchart for
Master Receive Mode
(Example)
18.4 Usage Notes
850
Table 18-7 Permissible SCL
Rise Time (t_Sr) Values
851
Table 18-8 I²C Bus Timing
(with Maximum Influence of
t _Sr/t_Sf )
854 to 857 • Notes on IRIC Flag
Clearance when Using Wait
Function
ø = 28 MHz portion added to
time indication [ns]
ø = 28 MHz portion added to
time indication [ns] and
values amended
Newly added
• Notes on ICDR Reads and
ICCR Access in Slave
Transmit Mode
• Notes on TRS Bit Setting in
Slave Mode
• Notes on ICDR Reads in
Transmit Mode and ICDR
Writes in Receive Mode
• Notes on ACKE Bit and TRS
Bit in Slave Mode
19.1.2 Block Diagram 860
Figure 19-1 Block Diagram
of A/D Converter
Note * added
19.2.2 A/D
864
Control/Status Register
(ADCSR)
Bit 7—A/D End Flag (ADF)
19.2.3 A/D Control 867
Register (ADCR)
Bits 7 and 6—Timer Trigger
Select 1 and 0 (TRGS1,
TRGS0)
19.5 Interrupts
876
Table 19-6 A/D Converter
Interrupt Source
Section 20 D/A
883
Converter
Title amended
21.1 Overview
891 to 893
H8S/2633R added after
H8S/2633 and H8S/2695
added after H8S/2631
21.2.1 System Control 892
Register (SYSCR)
Note * added
11