HD6432633 Datasheet, PDF (261/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.5.3 Address Multiplexing
In the case of DRAM space, the row address and column address are multiplexed. With address
multiplexing, the MXC1 and MXC0 bits of the MCR select the amount of shift in the row address.
Table 7-6 shows the relationship between MXC1 and MXC0 settings and the shift amount.
Table 7-6 MXC1 and MXC0 Settings vs Address Multiplexing
MCR
Shift
MXC1 MXC0 Amount
Address Pin
A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Row 0
0
8 bits
address
1
9 bits
A23 to A13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
1
0
10 bits
A23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1
Do not set —
—————————————
Column —
—
—
address
A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
7.5.4 Data Bus
Setting the ABWCR bit of an area set as DRAM space to 1 sets the corresponding area as 8-bit
DRAM space. Clearing the ABWCR bit to 0 sets the area as 16-bit DRAM. 16-bit DRAMs can be
directly connected in the case of 16-bit DRAM space.
With 8-bit DRAM space, the high data bus byte (D15 to D8) is valid. With 16-bit DRAM space,
the high and low data bus bytes (D15 to D0) are valid.
The access size and data alignment are the same as for the standard bus interface. See section
7.4.2, Data Size and Data Alignment for details.
207