HD6432633 Datasheet, PDF (651/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 11-53 shows the timing in this case.
ø
Address
Read signal
Input capture
signal
TGR
Internal
data bus
TGR read cycle
T1
T2
TGR address
X
M
M
Figure 11-53 Contention between TGR Read and Input Capture
597