HD6432633 Datasheet, PDF (1340/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

ICSR0—I²C Bus Status Register
H'FF79
ICSR1—I²C Bus Status Register
H'FF81
(These functions are not available in the H8S/2695.)
Bit
:
Initial value :
R/W
:
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
0
ACKB
0
R/W
Acknowledge bit
0 When receiving, 0 is output at acknowledge output timing.
When transmitting, this bit shows that an acknowledge (0)
has not been sent from the receiving device.
1 When receiving, 1 is output at acknowledge output timing.
When transmitting, this bit shows that an acknowledge (1)
has been sent from the receiving device.
General call address confirmation flag
0 General call address not confirmed
[Clearing conditions]
(1) When data is written to ICDR (when sending), or when data is
read from ICDR (when receiving)
(2) When 0 is written after reading ADZ=1
(3) In master mode
1 General call address confirmation
[Setting condition]
• When general call address is detected is in slave receive mode and
FSX = 0 or FS = 0).
Slave address confirmation flag
0 Slave address or general call address not confirmed
[Clearing conditions]
(1) When data is written to ICDR (when sending), or when data is
read from ICDR (when receiving)
(2) When 0 is written after reading AAS=1
(3) In master mode
1 Slave address or general call address confirmed
[Setting condition]
• When slave address or general call address is detected in slave
receive mode and FS = 0.
Arbitration lost flag
0 Secure bus.
[Clearing conditions]
(1) When data is written to ICDR (when sending), or when data is read (when
receiving)
(2) When 0 is written after reading AL=1
1 Bus arbitration lost
[Setting conditions]
(1) When there is a mismatch between internal SDA and SDA pin at rise in SCL
in master transmit mode
(2) When the internal SCL level is HIGH at the fall in SCL in master transmit mode.
2nd slave address confirmation flag
0 2nd slave address not confirmed
[Clearing conditions]
(1) When 0 is written after reading AASX=1
(2) When start conditions are detected
(3) In master mode
1 2nd slave address confirmed
[Setting condition]
• When 2nd slave address is detected in slave receive mode and FSX = 0.
I²C bus interface continuous transmit and receive interrupt request flag
0 Transmit wait state, or transmitting
[Clearing conditions]
(1) When 0 written after reading IRTR=1
(2) When IRIC flag is cleared to 0
1 Continuous transmit state
[Setting conditions]
• In I2C bus interface slave mode
When 1 is set in TDRE or RDRF flag when AASX=1.
• In other than I2C bus interface slave mode
When TDRE or RDRF flag is set to 1.
Normal end condition detection flag
0 No normal end condition
[Clearing conditions]
(1) When 0 is written after reading STOP=1
(2) When IRIC flag is cleared to 0
1 Normal end condition detected in slave mode in I²C bus format
[Setting condition]
On detection of stop condition on completion of sending frame.
• No meaning when in other than slave mode in I²C bus format
Error stop condition detection flag
0 No error stop condition
[Clearing conditions]
(1) When 0 written after reading ESTP=1
(2) When IRIC flag is cleared to 0
1 • Error stop condition detected in slave mode in I2C bus format
[Setting condition]
On detection of stop condition while sending frame.
• No meaning when in other than slave mode in I2C bus format
Note: * Only 0 can be written to these bits (to clear these flags).
1286
IIC0
IIC1