HD6432633 Datasheet, PDF (970/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1
enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
Bit 3
FLSHE
0
1
Description
Flash control registers deselected in area H'FFFFA8 to H'FFFFAC
Flash control registers selected in area H'FFFFA8 to H'FFFFAC
(Initial value)
Bits 2 to 0—Reserved: Should always be written with 0.
22.6 On-Board Programming Modes
When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
22-9. For a diagram of the transitions to the various flash memory modes, see figure 22-11.
Table 22-9 Setting On-Board Programming Modes
Mode
Boot mode
User program mode
Expanded mode
Single-chip mode
Expanded mode
Single-chip mode
FWE
1
1
MD2
0
0
1
1
MD1
1
1
1
1
MD0
0
1
0
1
916