HD6432633 Datasheet, PDF (234/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
0
1
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port
Wait input by WAIT pin enabled
(Initial value)
7.2.6 Pin Function Control Register (PFCR)
Bit
:
7
6
5
4
3
2
1
0
CSS07 CSS36 BUZZE* LCASS* AE3
AE2
AE1
AE0
Initial value :
0
0
0
0
1/0
1/0
0
1/0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * This function is not available in the H8S/2695. Only 0 should be written to the BUZZE
and LCASS bits.
PFCR is an 8-bit read/write register that controls the CS selection of pins PG4 and PG1, controls
LCAS selection of pins PF2 and PF6, and controls the address output in expanded mode with
ROM.
PFCR is initialized to H'0D/H'00 by a power-on reset and in hardware standby mode. It retains its
previous state by a manual reset or in software standby mode.
Bit 7—CS0/CS7 Select (CSS07): This bit selects the contents of CS output via the PG4 pin. In
modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS.
Bit 7
CSS07
0
1
Description
Selects CS0
Selects CS7
(Initial value)
Bit 6—CS3/CS6 Select (CSS36): This bit selects the contents of CS output via the PG1 pin. In
modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS.
Bit 6
CSS36
0
1
Description
Selects CS3
Selects CS6
(Initial value)
180