HD6432633 Datasheet, PDF (144/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

2.8.4 Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5 Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.
Bus masters other than the CPU are DMA controller (DMAC)* and data transfer controller
(DTC)*.
For further details, refer to section 7, Bus Controller.
Note: * DMAC and DTC functions are not available in the H8S/2695.
2.8.6 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode*¹, and watch mode*¹. There are
also three other power-down modes: medium-speed mode, module stop mode, and subactive
mode*¹. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock.
Module stop mode permits halting of the operation of individual modules, other than the CPU.
Subactive mode*¹, subsleep mode*¹, and watch mode*¹ are power-down states using subclock
input. For details, refer to section 24, Power-Down Modes.
(1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while
the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep
mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of
CPU registers are retained.
(2) Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is set
to 0, and the PSS bit in TCSR (WDT1)*² is set to 0. In software standby mode, the CPU and
clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of
CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states.
(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY
pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop.
The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip
RAM contents are retained.
Notes: *1 This function is not available in the H8S/2695.
*2 WDT1 is not available in the H8S/2695.
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