HD6432633 Datasheet, PDF (691/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3)
TCSR0
Bit
:
Initial value:
R/W
:
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSR1, TCSR3
Bit
:
7
6
5
4
CMFB CMFA OVF
—
Initial value :
0
0
0
1
R/W
: R/(W)* R/(W)* R/(W)* —
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSR2
Bit
:
7
6
5
4
CMFB CMFA OVF
—
Initial value :
0
0
0
0
R/W
: R/(W)* R/(W)* R/(W)* R/W
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 to TCSR3 are 8-bit registers that display compare match and timer overflow statuses, and
control compare match output.
TCSR0 and TCSR2 are initialized to H'00, and TCSR1 and TCSR3 to H'10, by a reset and in
hardware standby mode.
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