HD6432633 Datasheet, PDF (211/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits
specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked.
Bit 5
Bit 4
Bit 3
BAMRA2 BAMRA1 BAMRA0 Description
0
0
0
All BARA bits are unmasked and included in break conditions
(Initial value)
1
BAA0 (lowest bit) is masked, and not included in break
conditions
1
0
BAA1–0 (lower 2 bits) are masked, and not included in break
conditions
1
BAA2–0 (lower 3 bits) are masked, and not included in break
conditions
1
0
0
BAA3–0 (lower 4 bits) are masked, and not included in break
conditions
1
BAA7–0 (lower 8 bits) are masked, and not included in break
conditions
1
0
BAA11–0 (lower 12 bits) are masked, and not included in break
conditions
1
BAA15–0 (lower 16 bits) are masked, and not included in break
conditions
Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an
instruction fetch, data read, data write, or data read/write cycle as the channel A break condition.
Bit 2
CSELA1
0
1
Bit 1
CSELA0
0
1
0
1
Description
Instruction fetch is used as break condition
Data read cycle is used as break condition
Data write cycle is used as break condition
Data read/write cycle is used as break condition
(Initial value)
Bits 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.
Bit 0
BIEA
0
1
Description
PC break interrupts are disabled
PC break interrupts are enabled
(Initial value)
157