HD6432633 Datasheet, PDF (721/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Table 14-4 Settings and Operation (Examples when ø = 10 MHz)
Fixed DADR Bits
Bit Data
Resolution
Base
Conversion T_L (if OS = 0)
CKS T (µs)
CFS Cycle (µs) Cycle (µs) T_H (if OS = 1)
Precision
Conversion
(Bits) 3 2 1 0 Cycle* (µs)
0 0.1
0 6.4
1638.4
1. Always low (or high) 14
1638.4
(DADR = H'0001 to
H'03FD)
2. (Data value) × T 12
(DADR = H'0401 to
H'FFFD)
0 0 409.6
10
0 0 0 0 102.4
1 25.6
1638.4
1. Always low (or high) 14
(DADR = H'0003 to
H'00FF)
1638.4
2. (Data value) × T 12
(DADR = H'0103 to
H'FFFF)
0 0 409.6
10
0 0 0 0 102.4
1 0.2
0 12.8
3276.8
1. Always low (or high) 14
(DADR = H'0001 to
H'03FD)
3276.8
2. (Data value) × T 12
(DADR = H'0401 to
H'FFFD)
0 0 819.2
10
0 0 0 0 204.8
1 51.2
3276.8
1. Always low (or high) 14
(DADR = H'0003 to
H'00FF)
3276.8
2. (Data value) × T 12
(DADR = H'0103 to
H'FFFF)
0 0 819.2
10
0 0 0 0 204.8
Note: * This column indicates the conversion cycle when specific DADR bits are fixed.
667