HD6432633 Datasheet, PDF (848/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the
DMAC* or DTC*. If an error occurs, an error flag is set but the RDRF flag is not. Consequently,
the DTC* or DTC* is not activated, but instead, an ERI interrupt request is sent to the CPU.
Therefore, the error flag should be cleared.
Notes: For block transfer mode, see section 16.4, SCI Interrupts.
* DMAC and DTC functions are not available in the H8S/2695.
17.3.7 Operation in GSM Mode
Switching the Mode: When switching between smart card interface mode and software standby
mode, the following switching procedure should be followed in order to maintain the clock duty.
• When changing from smart card interface mode to software standby mode
[1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to
the value for the fixed output state in software standby mode.
[2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
operation. At the same time, set the CKE1 bit to the value for the fixed output state in software
standby mode.
[3] Write 0 to the CKE0 bit in SCR to halt the clock.
[4] Wait for one serial clock period.
During this interval, clock output is fixed at the specified level, with the duty preserved.
[5] Make the transition to the software standby state.
• When returning to smart card interface mode from software standby mode
[6] Exit the software standby state.
[7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
normal duty.
Normal operation
Software
standby
Normal operation
[1] [2] [3]
[4] [5]
[6] [7]
Figure 17-9 Clock Halt and Restart Procedure
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