HD6432633 Datasheet, PDF (233/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 4—OE Select (OES): Selects the CS3 pin as the OE pin.
Bit 4
OES
0
1
Description
Uses the CS3 pin as the port or as CS3 signal output
When only area 2 is set for DRAM, or when areas 2 to 5 are set as
contiguous DRAM space, the CS3 pin is used as the OE pin
(Initial value)
Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the
DMAC single address transfer bus timing.
Bit 3
DDS
0
1
Description
When performing DMAC single address transfers to DRAM, always execute full
access. The DACK signal is output as a low-level signal from the T_r or T₁ cycle
Burst access is also possible when performing DMAC single address
tranfers to DRAM. The DACK signal is output as a low-level signal
from the T_C1 or T₂ cycle
(Initial value)
Bit 2—Read CAS Timing Select (RCTS): Selects the CAS signal output timing.
Bit 2
RCTS
0
1
Description
CAS signal output timing is same when reading and writing
(Initial value)
When reading, CAS signal is asserted half cycle earlier than when writing
Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write
buffer function in the external write cycle or the DMAC* single address cycle.
Bit 1
WDBE
0
1
Description
Write data buffer function not used
Write data buffer function used
(Initial value)
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