HD6432633 Datasheet, PDF (714/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS
0
1
Description
Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
(Initial value)
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
0
1
Description
DADRA and DADRB can be accessed
DACR and DACNT can be accessed
(Initial value)
14.2.3 PWM D/A Control Register (DACR)
Bit
:7
6
5
TEST PWME —
Initial value : 0
0
1
R/W
: R/W
R/W
—
4
3
2
1
0
—
OEB OEA
OS
CKS
1
0
0
0
0
—
R/W
R/W
R/W
R/W
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
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