HD6432633 Datasheet, PDF (232/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.2.5 Bus Control Register L (BCRL)
Bit
:
Initial value :
R/W
:
7
6
5
BRLE BREQOE —
0
0
0
R/W R/W
—
4
OES*
0
R/W
Note: * This function is not available in the H8S/2695.
3
DDS*
1
R/W
2
RCTS*
0
R/W
1
WDBE
0
R/W
0
WAITE
0
R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized
by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Description
External bus release is disabled. BREQ, BACK and BREQO can be used as I/O ports
(Initial value)
External bus release is enabled
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Description
BREQO output disabled. BREQO can be used as I/O port
BREQO output enabled
(Initial value)
Bit 5—Reserved: This bit cannot be modified and is always read as 0.
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