HD6432633 Datasheet, PDF (285/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

(4) Notes
The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example,
if the 2nd of successive reads of different areas is a DRAM access, only the T_P cycle is inserted,
not the T₁ cycle. Figure 7-36 shows the timing. Note, however, that ICIS0 and ICIS1 settings are
valid in burst access in RAS down mode, and an idle cycle is inserted. Figure 7-37 (a) and (b)
shows the timing.
External read
DRAM space read
T₁
T₂
T₃
T_p
T_r
T_c1 T_c2
ø
Address bus
RD
Data bus
Figure 7-36 Example of DRAM Access after External Read
EXTAL
Address
RD
RAS
CAS, LCAS
Data bus
DRAM space read
Tp
Tr
Tc1
Tc2
External read
T1
T1
T2
T3
DRAM space read
Tc1
Tc1
Tc2
Idle cycle
Figure 7-37 (a) Example Idle Cycle Operation in RAS Down Mode (ICIS1=1)
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