HD6432633 Datasheet, PDF (269/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

This LSI
(address shift set to 10 bits)
CS2 (RAS)
CAS
LCAS
HWR (WE)
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
D15 to D0
CS3 (OE)
2CAS 16-Mbit DRAM
1MB × 16-bit configuration
10-bit column address
RAS
UCAS
LCAS
WE
A9
A8
A7
A6 _{(Row address input: A9 to A0)}
A5 ^{(Column address input: A9 to A0)}
A4
A3
A2
A1
A0
D15 to D0
OE
Figure 7-21 Example Connection of EDO Page Mode DRAM (OES=1)
7.5.10 Burst Operation
In addition to full DRAM access (normal DRAM access), in which the row address is output each
time the data in DRAM is accessed, there is also a high-speed page mode that allows high-speed
access (burst access). In this method, if the same row address is accessed successively, the row
address is output once and then only the column address is changed. Burst access is selected by
setting the BE bit of the MCR to 1.
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