HD6432633 Datasheet, PDF (1334/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

DMABCR—DMA Band Control Register
H'FF66
(This function is not available in the H8S/2695.)
Short address mode
Bit
:
DMABCRH :
Initial value :
R/W
:
15
FAE1
0
R/W
14
FAE0
0
R/W
13
SAE1
0
R/W
12
SAE0
0
R/W
11
DTA1B
0
R/W
10
DTA1A
0
R/W
9
DTA0B
0
R/W
8
DTA0A
0
R/W
DMAC
Single address enable 0
0
Transfer in dual address mode.
1
Transfer in single address mode.
Single address enable 1
0
Transfer in dual address mode.
1
Transfer in single address mode.
Full address enable 0
0
Short address mode.
1
Full address mode.
Full address enable 1
0
Short address mode.
1
Full address mode.
Data transfer acknowledge 1B
0
Clearing of selected internal interrupt factor at DMA transfer disabled.
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
Data transfer acknowledge 1A
0
Clearing of selected internal interrupt factor at DMA transfer disabled.
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
Data transfer acknowledge 0B
0
Clearing of selected internal interrupt factor at DMA transfer disabled.
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
Data transfer acknowledge 0A
0
Clearing of selected internal interrupt factor at DMA transfer disabled.
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
Bit
:
DMABCRL :
Initial value :
R/W
:
7
DTE1B
0
R/W
6
DTE1A
0
R/W
5
DTE0B
0
R/W
4
3
2
1
0
DTE0A DTIE1B DTIE1A DTIE0B DTIE0A
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Data transfer enable 0A
0
Data transfer disabled.
1
Data transfer enabled.
Data transfer enable 0B
0
Data transfer disabled.
1
Data transfer enabled.
Data transfer enable 1A
0
Data transfer disabled.
1
Data transfer enabled.
Data transfer enable 1B
0
Data transfer disabled.
1
Data transfer enabled.
Data transfer interrupt enable 1B
0
Transfer end interrupt disabled.
1
Transfer end interrupt enabled.
Data transfer interrupt enable 1A
0
Transfer end interrupt disabled.
1
Transfer end interrupt enabled.
Data transfer interrupt enable 0B
0
Transfer end interrupt disabled.
1
Transfer end interrupt enabled.
Data transfer interrupt enable 0A
0
Transfer end interrupt disabled.
1
Transfer end interrupt enabled.
1280