HD6432633 Datasheet, PDF (126/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Type
Arithmetic
operations
Logic
operations
Instruction
CLRMAC
LDMAC
STMAC
AND
OR
XOR
NOT
Shift
operations
SHAL
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Bit-
manipulation
instructions
BSET
BCLR
BNOT
Size*¹
—
L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
B
B
B
Function
0 → MAC
Clears the multiply-accumulate register to zero.
Rs → MAC, MAC → Rd
Transfers data between a general register and a
multiply-accumulate register.
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
¬ (Rd) → (Rd)
Takes the one's complement of general register
contents.
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
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