HD6432633 Datasheet, PDF (270/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

(1) Operation Timing for Burst Access (High-Speed Page Mode)
Figure 7-22 shows the operation timing for burst access. When the DRAM space is successively
accessed, the CAS signal and column address output cycle (2 states) are continued as long as the
row address is the same in the preceding and succeeding access cycles. The MXC1 and MXC0
bits of the MCR specify which row address is compared.
T_p
ø
A23 to A0
AS
CSn (RAS)
CAS, LCAS
Read
HWR (WE)
OE^*
D15 to D0
T_r
T_c1
T_c2
T_c1
T_c2
row
column1
column2
RCTS= 0
RCTS= 1
CAS, LCAS
Write
HWR (WE)
OE
D15 to D0
Notes: n=2 to 5
* OE is enabled when OES=1.
Figure 7-22 Operating Timing in High-Speed Page Mode
The bus cycle can also be extended in burst access by inserting wait states. The method and timing
of inserting the wait states is the same as in full access. For details, see section 7.5.8, Wait Control.
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