HD6432633 Datasheet, PDF (221/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.1.2 Block Diagram
Figure 7-1 shows a block diagram of the bus controller.
CS0 to CS7
Area decoder
External bus control signals
BREQ
BACK
BREQO
ABWCR
ASTCR
BCRH
BCRL
Bus
controller
Internal
address bus
Internal control
signals
Bus mode signal
WAIT
Wait
controller
WCRH
WCRL
External DRAM
control signal
DRAM controller
MCR*
DRAMCR*
RTCNT*
RTCOR*
Bus arbiter
CPU bus request signal
DTC* bus request signal
DMAC* bus request signal
CPU bus acknowledge signal
DTC* bus acknowledge signal
DMAC* bus acknowledge signal
Legend:
ABWCR : Bus width control register
ASTCR : Access state control register
BCRH : Bus control register H
BCRL : Bus control register L
WCRH : Wait control register H
WCRL : Wait control register L
MCR*
: Memory control register
DRAMCR* : DRAM control register
RTCNT* : Refresh timer counter
RTCOR* : Refresh time constand register
Note: * This function is not available in the H8S/2695.
Figure 7-1 Block Diagram of Bus Controller
167