HD6432633 Datasheet, PDF (534/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Port B Data Register (PBDR)
Bit
:
Initial value :
R/W
:
7
PB7DR
0
R/W
6
PB6DR
0
R/W
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains
its prior state by a manual reset or in software standby mode.
Port B Register (PORTB)
Bit
:
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value : —*
—*
—*
—*
—*
—*
—*
—*
R/W
:
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PB7 to PB0.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB7 to PB0) must always be performed on PBDR.
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B
read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin
states, as PBDDR and PBDR are initialized. PORTB retains its prior state in software standby
mode.
480