MC68030 Datasheet, PDF (91/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Set Summary
3.2.10 Memory Management Unit Instructions
The PFLUSH instructions flush the address translation caches (ATCs) and can optionally
select only nonglobal entries for flushing. PTEST performs a search of the address
translation tables, storing results in the MMU status register and loading the entry into the
ATC. Table 3–10 summarizes these instructions.
Instruction
PFLUSHA
PFLUSHA.N
PFLUSH
PFLUSH.N
PTEST
Operand Syntax
none
none
(An)
(An)
(An)
Table 3-10. MMU Instructions
Operand Size
none
none
none
none
none
Operation
Invalidate all ATC entries
Invalidate all nonglobal ATC entries
Invalidate ATC entries at effective address
Invalidate nonglobal ATC entries at effective address
Information about logical address → MMU status register
3.2.11 Multiprocessor Instructions
The TAS, CAS, and CAS2 instructions coordinate the operations of processors in
multiprocessing systems. These instructions use read-modify-write bus cycles to ensure
uninterrupted updating of memory. Coprocessor instructions control the coprocessor
operations. Table 3–11 lists these instructions.
Table 3-11. Multiprocessor Operations (Read-Modify-Write)
Instruction
CAS
CAS2
TAS
cpBcc
cpDBcc
cpGEN
cpRESTORE
cpSAVE
cpScc
cpTRAPcc
Operand Syntax
Dc,Du,〈ea〉
Dc1:Dc2,Du1:Du2,(
Rn):(Rn)
〈ea〉
〈label〉
label,Dn
User Defined
〈ea〉
〈ea〉
〈ea〉
none
#〈data〉
Operand Size
Operation
Read-Modify-Write
8, 16, 32
destination — Dc → CC; if Z then Du → destination
else destination→Dc
8, 16, 32
dual operand CAS
8
destination — 0; set condition codes; 1 → destination [7]
Coprocessor
16, 32
if cpcc true, then PC + d → PC
16
if cpcc false then Dn –1 → Dn
if Dn ≠ –1, then PC + d → PC
User Defined operand → coprocessor
none
restore coprocessor state from 〈ea〉
none
save coprocessor state at 〈ea〉
8
if cpcc true, then 1's → destination; else 0's → destination
none
if cpc true, then TRAPcc exception
16, 32
MOTOROLA
MC68030 USER’S MANUAL
3-13