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MC68030 Datasheet, PDF (523/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR
Applications Information
VCC
DSACK0
1
74F00
2
3
DSACK1
VCC
2
D
4 74F74
SD
5
Q
DSQ0
3 CP
CD
6
Q
1
12 D
10 74F74
SD
Q9
DSQ1
CLK
AS
RESET
STATUS
REFILL
VCC
STERM
ECS
11
CP
8
Q
CD
13
74F114
4 SD1
10 SD2
3 J1
2 K1
13 CP
11 J2
12 K2 CD
Q1 5
Q1 6
Q2 9
Q2 8
1
VCC
4 74F74
SD
2
D
Q5
3
CP
6
Q
CD
1
74F00
4
6 DSACK
5
DSACK
CLK
AS
RESET
STATUSQ
REFILLQ
ECSQ
STERMQ
VCC
12
D
10 74F74
SD
Q9
11
CP
Q8
CD
13
ECSQ
VCC
PAL 16R6D
20 VCC
2
3I
4I
5
I
I
6I
7I
8I
9I
1 CP
11 OE
10
V SS
Q 18
Q 17
Q 16
Q 15
Q 14
Q 13
10 19
10 12
SECS
CLKOUT
PHALT
FILL
EP
IE
SAMPLE
4
74F00
6
5
ECSC
FIG 12-15
Figure 12-15. Example 3-1-1-1 Pipelined Burst Mode Memory Bank at
20 MHz, 256K Bytes
The structure of this memory bank is very similiar to the 2-1-1-1 memory bank described in
12.5.2 A 2-1-1-1 Burst Mode Memory Bank Using SRAMS. In fact, the PAL and address
buffers are exactly the same. The PAL equations are provided in Figure 12-10. The most
important differences occur in the data latches, which are now flip-flops. Also, the D-type flip-
flop has been moved from the input side of the PAL to the TERM output.
The data flip-flops allow the long words out of the memory to be pipelined such that setup
and hold times are easier to satisfy. The memory devices are generating the next long word
of data even before the MC68030 has latched the “current”long word. This alteration eases
access timing requirements such that 35-ns memory can be used with a clock frequency of
20 MHz. If the clock frequency is less than 17 MHz, 45-ns memory can be used. Another
benefit of the slower cycle is a relaxed timing requirement for the enable inputs of the
SRAMs. Although Figure 12-15 has all the SRAM chip enables grounded, the timing in this
design will be preserved if the memory's E signal is asserted within 10 ns after the rising
edge of state S2. Figure 12-16 shows four possible enable circuits.
(UNABLE TO LOCATE ART)
Figure 12-16. Additional Memory Enable Circuits
MOTOROLA
MC68030 USER’S MANUAL
12-27