MC68030 Datasheet, PDF (475/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.8 Arithmetical/Logical Instructions
The arithmetical/logical operation timing table indicates the number of clock periods needed
for the processor to perform the specified arithmetical/logical instruction using the specified
addressing mode. Footnotes indicate when to account for the appropriate fetch effective
address or fetch immediate effective address times. For instruction-cache case and for no-
cache case, the total number of clock cycles is outside the parentheses. The number of
read, prefetch, and write cycles is given inside the parentheses as (r/p/w). The read,
prefetch, and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
ADD
ADDA.W
ADDA.L
ADD
ADD.W
ADDA.L
ADD
AND
AND
AND
EOR
EOR
OR
OR
OR
SUB
SUB
Instruction
Rn,Dn
Rn,An
Rn,An
EA,Dn
EA,An
EA,An
Dn,EA
Dn,Dn
EA,Dn
Dn,EA
Dn,Dn
Dn,EA
Dn,Dn
EA,Dn
Dn,EA
Rn,Dn
EA,Dn
Head
2
4
2
0
0
0
0
2
0
0
2
0
2
0
0
2
0
Tail
I-Cache Case No-Cache Case
0
2(0/0/0)
2(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
2(0/0/0)
2(0/1/0)
0
2(0/0/0)
2(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
0
2(0/0/0)
2(0/1/0)
1
3(0/0/1)
4(0/1/1)
0
2(0/0/0)
2(0/1/0)
0
2(0/0/0)
2(0/1/0)
11-40
MC68030 USER’S MANUAL
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