MC68030 Datasheet, PDF (376/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
The first word of the cpScc instruction is the F-line operation word. This word contains the
CpID field in bits [9-11] and 001 in bits [8:6] to identify the cpScc instruction. The lower six
bits of the F-line operation word are used to encode an M68000 Family effective addressing
mode (refer to 2.5 Effective Address Encoding Summary).
The second word of the cpScc instruction format contains the coprocessor condition
selector in bits [0-5]. Bits [6-15] of this word are reserved by Motorola and should be zero to
ensure compatibility with future M68000 products. This word is written to the condition CIR
to initiate the cpScc instruction.
If the coprocessor requires additional information to evaluate the condition, the instruction
can include extension words to provide this information. The number of these extension
words, which follow the word containing the coprocessor condition selector field, is
determined by the coprocessor design.
The final portion of the cpScc instruction format contains zero to five effective address
extension words. These words contain any additional information required to calculate the
effective address specified by bits [0-5] of the F-line operation word.
10.2.2.2.2 Protocol. Figure 10-8 shows the protocol for the cpScc instruction. The
MC68030 transfers the condition selector to the coprocessor by writing the word 22following
the F-line operation word to the condition CIR. The main processor then reads the response
CIR to determine its next action. The coprocessor can return a response primitive to request
services necessary to evaluate the condition. The operation of the cpScc instruction
depends on the condition evaluation indicator returned to the main processor by the
coprocessor. When the coprocessor returns the false condition indicator, the main
processor evaluates the effective address specified by bits [0-5] of the F-line operation word
and sets the byte at that effective address to FALSE (all bits cleared). When the coprocessor
returns the true condition indicator, the main processor sets the byte at the effective address
to TRUE (all bits set to one).
10-16
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