MC68030 Datasheet, PDF (519/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
12.5.2 A 2-1-1-1 Burst Mode Memory Bank Using SRAMS
The MC68030 normally attains its lowest bus utilization when the external memory system
can support a 2-1-1-1 burst protocol. However, exceptions to this can occur. For instance,
when a large amount of memory accesses are not governed by the locality of reference
principles, burst accesses may not decrease bus utilization. This section describes a
complete 2-1-1-1 memory bank with 256K bytes that can operate with a 20-MHz MC68030.
Nonburst reads and all write cycles execute in two clocks.
Figure 12-14 shows the complete memory bank and its connection to the MC68030. The
required parts include:
(32) 64K x 1 SRAMs 25 ns access time (Motorola's MCM6287-25 or equivalent)
(2) 74ALS244 buffers
(4) 74AS373 latches
(2) 74F32 OR gates
(4) 74F191 counters
(1) PAL16L8D (or equivalent)
(1) 74F04 inverter
The system must also provide any STERM or CBACK consolidation circuitry as required
(e.g., due to the presence of multiple synchronous memory banks or ports). In Figure 12-14,
this consolidation circuitry is shown as an AND gate.
The memory bank can be divided into four sections:
1. The byte select and address decode section (provided by the PAL).
2. The burst address generator (provided by the counters).
3. The actual memory section (SRAMs).
4. The buffer section (address and data).
MOTOROLA
MC68030 USER’S MANUAL
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