 English |
|
|
|
|
|
|
|
| MC68030 Datasheet, PDF (462/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR | |||
| |||
| ◁ |
11.6.1 Fetch Effective Address (fea) (Continued)
Instruction Execution Timing
Address Mode
Head
Tail
I-Cache Case No-Cache Case
FULL FORMAT EXTENSION WORD(S)
(d16,An) or (d16,PC)
2
(d16,An,Xn) or (d16,PC,Xn)
4
([d16,An]) or ([d16,PC])
2
([d16,An],Xn) or ([d16,PC],Xn)
2
[d16,An],d16) or ([d16,PC],d16)
2
([d16,An],Xn,d16) or ([d16,PC],Xn,d16)
2
([d16,An],d32) or ([d16,PC],d32)
2
([d16,An],Xn,d32) or ([d16,PC],Xn,d32)
2
(B)
4
(d16,B)
4
(d32,B)
4
([B])
4
([B],I)
4
([B],d16)
4
([B],I,d16)
4
([B],d32)
4
([B],I,d32)
4
([d16,B])
4
([d16,B],I)
4
([d16,B],d16)
4
([d16B],I,d16)
4
([d16,B],d32)
4
([d16,B\,I,d32)
4
([d32,B])
4
([d32,B],I)
4
([d32,B],d16)
4
([d32,B],I,d16)
4
([d32,B],d32)
4
([d32,B],I,d32)
4
0
6(1/0/0)
0
6(1/0/0)
0
10(2/0/0)
0
10(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
6(1/0/0)
0
8(1/0/0)
0
12(1/0/0)
0
10(2/0/0)
0
10(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
12(2/0/0)
0
14(2/0/0)
0
14(2/0/0)
0
14(2/0/0)
0
14(2/0/0)
0
16(2/0/0)
0
16(2/0/0)
0
18(2/0/0)
0
18(2/0/0)
0
18(2/0/0)
0
18(2/0/0)
B = Base Address; 0, An, PC, Xn, An+Xn, PC+Xn. Form does not affect timing.
I = Index; 0, Xn
% = No clock cycles incurred by effective address fetch.
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
7(1/1/0)
7(1/1/0)
10(2/1/0)
10(2/1/0)
13(2/2/0)
13(2/2/0)
14(2/2/0)
14(2/2/0)
7(1/1/0)
10(1/1/0)
13(1/2/0)
10(2/1/0)
10(2/1/0)
13(2/1/0)
13(2/1/0)
14(2/2/0)
14(2/2/0)
13(2/1/0)
13(2/1/0)
16(2/2/0)
16(2/2/0)
17(2/2/0)
17(2/2/0)
17(2/2/0)
17(2/2/0)
20(2/2/0)
20(2/2/0)
21(2/3/0)
21(2/3/0)
MOTOROLA
MC68030 USERâS MANUAL
11-27
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese