MC68030 Datasheet, PDF (443/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
HEAD
CACHE CASE
BEST CASE
READ/WRITE BUS
TIME OR SYNC
MICROCODE TIME
WRITE BUS TIME
TAIL
Figure 11-3. Derivation of Instruction Overlap Time
The nature of the instruction overlap and the fact that the heads of some instructions equal
the total instruction-cache-case time for those instructions makes a zero net execution time
possible. The execution time of an instruction is completely absorbed by overlap with the
previous instruction.
11.3.3 Average No-Cache Case
The average no-cache-case (NCC) time for an instruction takes into account the time
required for the microcode to execute plus the time required for all external bus activity. This
time is calculated assuming both caches miss and the associated instruction prefetches
require one external bus cycle per two instruction prefetches. Refer to 11.2.2 Instruction
Pipe. The average no-cache-case time also assumes no overlap. All bus cycles are
assumed to take two clock periods. Average no-cache-case times for instructions and
effective address calculations are listed in 11.6 Instruction Timing Tables. Because the
no-cache-case times assume no overlap, the head and tail values listed in these tables do
not apply to the no-cache-case values.
Since the actual no-cache-case time depends on the alignment of prefetches associated
with an instruction, both alignment cases were considered, and the value shown in the table
is the average of the odd-word-aligned case and the even-word-aligned case (rounded up
to an integral number of clocks). Similarly, the number of prefetch bus cycles is the average
of these two cases rounded up to an integral number of bus cycles.
11-8
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