MC68030 Datasheet, PDF (505/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
CLK
VCC
AS
NC
FC2
NC
FC1
NC
FC0
PAL 16L8
NC
A19
10 ns
A13
A18
A14
A17
CLKD
A16
CS
GND
A15
Figure 12-3. Chip-Select Generation PAL
(UNABLE TO LOCATE ART)
Figure 12-4. PAL Equations
(UNABLE TO LOCATE ART)
Figure 12-5. Bus Cycle Timing Diagram
12.3 BYTE SELECT LOGIC FOR THE MC68030
The architecture of the MC68030 allows it to support byte, word, and long-word operand
transfers to any 8-, 16-, or 32-bit data port regardless of alignment. This feature allows the
programmer to write code that is not bus-width specific. When accessed, the peripheral or
memory subsystem reports its actual port size to the processor, and the MC68030 then
dynamically sizes the data transfer accordingly, using multiple bus cycles when necessary.
Hardware designers also have the flexibility to choose implementations independent of
software prejudices. The following paragraphs describe the generation of byte select control
signals that enable the dynamic bus sizing mechanism, the transfer of differently sized
operands, and the transfer of misaligned operands to operate correctly.
The following signals control the MC68030 operand transfer mechanism:
• A1, A0 = Address lines. The most significant byte of the operand to be transferred is
addressed directly.
• SIZ1, SIZ0 = Transfer size. Output of the MC68030. These indicate the number of
bytes of an operand remaining to be transferred during a given bus cycle.
• R/W = Read/Write. Output of the MC68030. For byte select generation in MC68030
systems, R/W must be included in the logic if the data from the device is cach-
able.
12-8
MC68030 USER’S MANUAL
MOTOROLA