MC68030 Datasheet, PDF (371/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
An instruction in the coprocessor general instruction category optionally includes a number
of extension words following the coprocessor command word. These words can provide
additional information required for the coprocessor instruction. For example, if the
coprocessor requests that the MC68030 calculate an effective address during coprocessor
instruction execution, information required for the calculation must be included in the
instruction format as effective address extension words.
10.2.1.2 PROTOCOL. The execution of a cpGEN instruction follows the protocol shown in
Figure 10-7. The main processor initiates communication with the coprocessor by writing the
instruction command word to the command CIR. The coprocessor decodes the command
word to begin processing the cpGEN instruction. Coprocessor design determines the
interpretation of the coprocessor command word; the MC68030 does not attempt to decode
it.
(UNABLE TO LOCATE ART)
Figure 10-7. Coprocessor Interface Protocol for
General Category Instructions
While the coprocessor is executing an instruction, it requests any required services from and
communicates status to the main processor by placing coprocessor response primitive
codes in the response CIR. After writing to the command CIR, the main processor reads the
response CIR and responds appropriately. When the coprocessor has completed the
execution of an instruction or no longer needs the services of the main processor to execute
the instruction, it provides a response to release the processor. The main processor can
then execute the next instruction in the instruction stream. However, if a trace exception is
pending, the MC68030 does not terminate communication with the coprocessor until the
coprocessor indicates that it has completed all processing associated with the cpGEN
instruction (refer to 10.5.2.5 Trace Exceptions).
The coprocessor interface protocol shown in Figure 10-7 allows the coprocessor to define
the operation of each general category instruction. That is, the main processor initiates the
instruction execution by writing the instruction command word to the command CIR and by
reading the response CIR to determine its next action. The execution of the coprocessor
instruction is then defined by the internal operation of the coprocessor and by its use of
response primitives to request services from the main processor. This instruction protocol
allows a wide range of operations to be implemented in the general instruction category.
10.2.2 Coprocessor Conditional Instructions
The conditional instruction category provides program control based on the operations of
the coprocessor. The coprocessor evaluates a condition and returns a true/false indicator
to the main processor. The main processor completes the execution of the instruction based
on this true/false condition indicator.
The implementation of instructions in the conditional category promotes efficient use of both
the main processor's and the coprocessor's hardware. The condition specified for the
instruction is related to the coprocessor operation and is, therefore, evaluated by the
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MC68030 USER’S MANUAL
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