MC68030 Datasheet, PDF (527/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
12.6.1 Cache Implementation
An example organization of an external cache is shown in Figure 12-15. With this
organization, the cache timing controller does not terminate a bus cycle until the cache has
had sufficient time to validate the access as a “hit”or a “miss”. When a hit decision is made,
the cache controller asserts the STERM signal and also blocks propagation of AS (A) to the
external system. If the cache decision cannot be completed before AS would normally be
asserted by the MC68030, some provision must be made to delay the propagation of AS
until the decision is valid. Otherwise, spurious assertions of the AS signal are likely to occur.
The cache control circuit (B) contains all logic required to clear or create cache entries. Also
contained in (B) is the decision logic required to determine whether a hit or miss has
occurred and the timing logic that is required to prevent propagation of the ``hit'' signal until
the lookup and compare circuitry has had sufficient time to generate a valid decision. The
critical path in the design of this cache is from the output of valid address by the MC68030
to the assertion of STERM by the cache controller (see Equation 12-3 of Table 12-2). After
a cache hit decision has been made, the hit signal directly drives the STERM signal.
Qualifying STERM with AS is not necessary assuming the appropriate setup and hold times
are respected when AS is asserted. Operating at 20 MHz with no wait states, 21 ns are
available from the presentation of valid address by the MC68030 to the assertion of STERM
by the cache controller while 46 ns are available from valid address to data valid at the
processor.
If the access times cannot be met due to the particular cache architecture, size, cost, or
other consideration, the system designer may choose to utilize an early termination
approach, as discussed above, that increases the decision time available to the cache
controller by meeting the critical path from address valid to BERR/HALT asserted (see
Equation 12-5 of Table 12-2). The only required changes to the cache structure shown in
Figure 12-17 is the generation of STERM. Figure 12-18 shows an example circuit that could
be positioned between the MC68030 and the external cache to provide the early termination
or late retry function.
MOTOROLA
MC68030 USER’S MANUAL
12-31