MC68030 Datasheet, PDF (225/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
S0
S2
Sw
Sw
Sw
S4
CLK
A31-A0
FC2-FC0
SIZ1-SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31-D0
BERR
S0
S2
S4
HALT
READ WITH BUS ERROR ASSERTED
INTERNAL
PROCESSING
STACK WRITE
Figure 7-48. Breakpoint Acknowledge Cycle Timing (Exception Signaled)
Another signal that is used for bus exception control is HALT. This signal can be asserted
by an external device for debugging purposes to cause single bus cycle operation or (in
combination with BERR) a retry of a bus cycle in error.
MOTOROLA
MC68030 USER’S MANUAL
7-79