MC68030 Datasheet, PDF (229/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
Table 7-9. STERM, BERR, and HALT Assertion Results
Case
No.
Control
Signal
1
STERM
BERR
HALT
2
STERM
BERR
HALT
3
STERM
BERR
HALT
4
STERM
BERR
HALT
5
STERM
BERR
HALT
6
STERM
BERR
HALT
Asserted on Rising
Edge of State
N
N+2
A
—
NA
—
NA
—
NA
A
NA
NA
A/S
S
NA
A
A/S
S
NA
NA
A
—
A
—
N/A
—
NA
A
A
S
A/S
S
A
—
A
—
A
—
Result
Normal cycle terminate and continue.
Normal cycle terminate and halt. Continue when HALT
negated.
Terminate and take bus error exception, possibly
deferred.
Terminate and take bus error exception, possibly
deferred.
Terminate and retry when HALT negated.
Terminate and retry when HALT negated.
LEGEND:
N
A
NA
X
S
—
—The number of current even bus state (e.g., S2, S4, etc.)
—Signal is asserted in this bus state
—Signal is not asserted in this state
—Don't care
—Signal was asserted in previous state and remains asserted in this state
—State N+2 not part of bus cycle
EXAMPLE A:
A system uses a watchdog timer to terminate accesses to an unpopulated address
space. The timer asserts BERR after timeout (case 3).
MOTOROLA
MC68030 USER’S MANUAL
7-83