MC68030 Datasheet, PDF (385/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
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CpID
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EFFECTIVE ADDRESS
EFFECTIVE ADDRESS EXTENSION WORDS (0-5 WORDS)
Figure 10-15. Coprocessor Context Save Instruction Format (cpSAVE)
The control alterable and predecrement addressing modes are valid for the cpSAVE
instruction. Other addressing modes cause the MC68030 to initiate F-line emulator
exception processing as described in 10.5.2.2 F-Line Emulator Exceptions.
The instruction can include as many as five effective address extension words following the
cpSAVE instruction operation word. These words contain any additional information
required to calculate the effective address specified by bits [0-5] of the operation word.
10.2.3.3.2 Protocol. Figure 10-16 shows the protocol for the coprocessor context save
instruction. The main processor initiates execution of the cpSAVE instruction by reading the
save CIR. Thus, the cpSAVE instruction is the only coprocessor instruction that begins by
reading from a CIR. (All other coprocessor instructions write to a CIR to initiate execution of
the instruction by the coprocessor.) The coprocessor communicates status information
associated with the context save operation to the main processor by placing coprocessor
format codes in the save CIR.
If the coprocessor is not ready to suspend its current operation when the main processor
reads the save CIR, it returns a “not ready'“ format code. The main processor services any
pending interrupts and then reads the save CIR again. After placing the not ready format
code in the save CIR, the coprocessor should either suspend or complete the instruction it
is currently executing.
MOTOROLA
MC68030 USER’S MANUAL
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