MC68030 Datasheet, PDF (449/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
Notice that the last instruction did not require the general Equation (11-2) since there were
no effective address (ea) additions. Therefore, Equation (11-1) is used:
CC_op5–min(H_op5,T_op4)
When using the fetch immediate effective address (fiea) or the calculate immediate effective
address (ciea) tables, the size of the data is significant in the timing calculations. For each
effective address, a line is listed for word data, #<data>.W, and for long data, #<data>.L.
The total head of some effective address types extends through the effective address
calculation and includes the head of the operation. These effective address calculations are
marked in the head column as follows:
X+op head
where:
X is the head of the effective address alone.
An example using the fiea table and the X+op head notation is:
Instruction
EORI.W
ADDI.L
#$400,-(A1)
#$6000FF,D1
Head
Tail
CC
1. EORI.W #$400,-(A1)
fiea #<data>.W,-(An)
2
2
4
EORI #<data>,Mem
2. ADDI.L #$6000FF,D1
fiea #<data>.L,D1
4+op head
0
4
6
0
4
ADDI #<data>,Dn
2(op head)
0
2
The following calculations use the general Equation (11-2):
Execution Time:
= CCea₁+[CCop₁-min(Hop₁,Tea₁]+[CCea₂- min(Hea₂,Top₁)]+
[CCop2-min(Hop2,Tea2)]
= 4+[3-min(0,2)]+[4-min(6,1)]+[2-min(2,0)]
= 4+3+3+2
= 2 clock periods
11-14
MC68030 USER’S MANUAL
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