MC68030 Datasheet, PDF (378/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.2.2.3.2 Protocol. Figure 10-8 shows the protocol for the cpDBcc instructions. The
MC68030 transfers the condition selector to the coprocessor by writing the word following
the operation word to the condition CIR. The main processor then reads the response CIR
to determine its next action. The coprocessor can use a response primitive to request any
services necessary to evaluate the condition. If the coprocessor returns the true condition
indicator, the main processor executes the next instruction in the instruction stream. If the
coprocessor returns the false condition indicator, the main processor decrements the low-
order word of the register specified by bits [0-2] of the F-line operation word. If this register
contains minus one (—1) after being decremented, the main processor executes the next
instruction in the instruction stream. If the register does not contain minus one (—1) after
being decremented, the main processor branches to the destination address to continue
instruction execution.
The MC68030 adds the displacement to the scanPC (refer to 10.4.1 ScanPC) to determine
the address of the next instruction. The scanPC must point to the 16-bit displacement in the
instruction stream when the destination address is calculated.
10.2.2.4 TRAP ON COPROCESSOR CONDITION. The trap on coprocessor condition
instruction allows the programmer to initiate exception processing based on conditions
related to the coprocessor operation.
10.2.2.4.1 Format. Figure 10-13 shows the format of the trap on coprocessor condition
instruction, denoted by the cpTRAPcc mnemonic.
15
14
13
12
11
98 7 6 5 4 3 2
0
1
1
1
1
CpID
001111
OPMODE
(RESERVED)
CONDITION SELECTOR
OPTIONAL COPRCESSOR-DEFINED EXTENSION WORDS
OPTIONAL WORD
OR LONG-WORD OPERAND
Figure 10-13. Trap On Coprocessor Condition (cpTRAPcc)
10-18
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