MC68030 Datasheet, PDF (467/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.3 Calculate Effective Address (cea) (Continued)
Address Mode
Head
Tail
I-Cache Case No-Cache Case
([d₁₆,B],d₃₂)
[d₁₆,B],I,d₃₂)
[d₁₆,B])
([d₁₆,B]I)
([d₁₆,B]d₁₆)
([d₁₆,B],I,d₁₆)
([d₁₆,B],d₃₂)
([d₁₆,B],I,d₃₂)
4
0
14(1/0/0)
4
0
14(1/0/0)
4
0
16(1/0/0)
4
0
16(1/0/0)
4
0
18(1/0/0)
4
0
18(1/0/0)
4
0
18(1/0/0)
4
0
18(1/0/0)
B = Base address; 0, An, PC, Xn, An+Xn, PC+Xn. Form does not affect timing.
I = Index; 0, Xn
% = No clock cycles incurred by effective address calculation.
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
16(1/2/0)
16(1/2/0)
17(1/2/0)
17(1/2/0)
20(1/2/0)
20(1/2/0)
20(1/3/0)
20(1/3/0)
11.6.4 Calculate Immediate Effective Address (ciea)
The calculate immediate effective address table indicates the number of clock periods
needed for the processor to fetch the immediate source operand and calculate the specified
destination effective address. In the case of two-word instructions, this table indicates the
number of clock periods needed for the processor to fetch the second word of the instruction
and calculate the specified source operand or single operand. Fetch time is only included
for the first level of indirection on memory indirect addressing modes. The effective
addresses are divided by their formats (refer to 2.5 Effective Address Encoding
Summary). For instruction-cache case and for no-cache case, the total number of clock
cycles is outside the parentheses. The number of read, prefetch, and write cycles is given
inside the parentheses as (r/p/w). The read, prefetch, and write cycles are included in the
total clock cycle number.
All timing data assumes two-clock reads and writes.
11-32
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