MC68030 Datasheet, PDF (304/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
Each logical portion of an entry has a corresponding 28-bit physical (or data) portion. The
physical portion contains these fields:
27
26
25
24 23
0
B
CI WP M
PHYSICAL ADDRESS
B — BUS ERROR
This bit is set for an entry if a bus error, an invalid descriptor, a supervisor violation, or a
limit violation is encountered during the table search corresponding to this entry. When B
is set, a subsequent access to the logical address causes the MC68030 to take a bus er-
ror exception. Since an ATC miss causes an immediate retry of the access after the table
search operation, the bus error exception is taken on the retry. The B bit remains set until
a PFLUSH instruction or a PLOAD instruction for this entry invalidates the entry or until
the replacement algorithm for the ATC replaces it.
CI — CACHE INHIBIT
This bit is set when the cache inhibit bit of the page descriptor corresponding to this entry
is set. When the MC68030 accesses the logical address of an entry with the CI bit set, it
asserts the cache inhibit out signal (CIOUT) during the corresponding bus cycle. This sig-
nal inhibits caching in the on-chip caches and can also be used for external caches.
WP — WRITE PROTECT
This bit is set when a WP bit is set in any of the descriptors encountered during the table
search for this entry. Setting a WP bit in a table descriptor write protects all pages access-
ed with that descriptor. When the WP bit is set, a write access or a read-modify-write ac-
cess to the logical address corresponding to this entry causes a bus error exception to be
taken immediately.
M — MODIFIED
This bit is set when a valid write access to the logical address corresponding to the entry
occurs. If the M bit is clear and a write access to this logical address is attempted, the
MC68030 aborts the access and initiates a table search, setting the M bit in the page de-
scriptor, invalidating the old ATC entry, and creating a new entry with the M bit set. The
MMU then allows the original write access to be performed. This assures that the first
write operation to a page sets the M bit in both the ATC and the page descriptor in the
translation tables even when a previous read operation to the page had created an entry
for that page in the ATC with the M bit clear.
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MC68030 USER’S MANUAL
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