MC68030 Datasheet, PDF (139/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

On-Chip Cache Memories
When a cachable read cycle provides data with both CIIN and BERR negated, the MC68030
attempts to fill the cache entry. Figure 6-5 shows the organization of a line of data in the
caches. The notation b0, b1, b2, and so forth identifies the bytes within the line. For each
entry in the line, a valid bit in the associated tag corresponds to a long-word entry to be
loaded. Since a single valid bit applies to an entire long word, a single entry mode operation
must provide a full 32 bits of data. Ports less than 32 bits wide require several read cycles
for each entry.
Figure 6-5 shows an example of a byte data operand read cycle starting at byte address $03
from an 8-bit port. Provided the data item is cachable, this operation results in four bus
cycles. The first cycle requested by the MC68030 reads a byte from address $03. The 8-bit
DSACKx response causes the MC68030 to fetch the remainder of the long word starting at
address $00. The bytes are latched in the following order: b3, b0, b1, and b2. Note that
during cache loading operations, devices must indicate the same port size consistently
throughout all cycles for that long-word entry in the cache.
Figure 6-6 shows the access of a byte data operand from a 16-bit port. This operation
requires two read cycles. The first cycle requests the byte at address $03. If the device
responds with a 16-bit DSACKx encoding, the word at address $02 (including the requested
byte) is accepted by the MC68030. The second cycle requests the word at address $00.
Since the device again responds with a 16-bit DSACKx encoding, the remaining two bytes
of the long word are latched, and the cache entry is filled.
(UNABLE TO LOCATE ART)
Figure 6-5. Single Entry Mode Operation — 8-Bit Port
(UNABLE TO LOCATE ART)
Figure 6-6. Single Entry Mode Operation — 16-Bit Port
With a 32-bit port, the same operation is shown in Figure 6-7. Only one read cycle is
required. All four bytes (including the requested byte) are latched during the cycle.
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Figure 6-7. Single Entry Mode Operation — 32-Bit Port
If a requested access is misaligned and spans two cache entries, the bus controller attempts
to fill both associated long-word cache entries. An example of this is an operand request for
a long word on an odd-word boundary. The MC68030 first fetches the initial byte(s) of the
operand (residing in the first long word) and then requests the remaining bytes to fill that
cache entry (if the port size is less than 32 bits) before it requests the remainder of the
operand and corresponding long word to fill the second cache entry. If the port size is 32
bits, the processor performs two accesses, one for each cache entry.
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MC68030 USER’S MANUAL
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