MC68030 Datasheet, PDF (516/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
The second section contains the memory devices. Eight devices are used, but some
designs may wish to increase this to support EDAC or to increase density. The most
important feature of the memory devices used in this design is the separate data-in and
data-out pins, which allow the SRAMs to be enabled before address decode is complete
without causing data bus contention. The enable pins on the SRAMs have been grounded
for both simplicity and improved memory access timing. If the designer wishes to include
some type of enable circuitry to take advantage of low bus utilization for lower power
consumption, the timing in this design will be preserved if the memory's E signal is asserted
before the falling edge of state S0 (at the same time as or before the address becomes
valid). Two possible enable circuits are shown in Figure 12-11.
INSTRUCTION
BOUNDARIES
CLK
REFILL
STATUS
FIG 12-11
Figure 12-11. Additional Memory Enable Circuits
The third section of the memory bank is the data buffers. The data buffers are shown as
74F244, but 74AS244s may also be used. The RDCS signal, qualified with AS, controls the
data buffers during read operations as described above.
To maximize performance, both read and write operations should be capable of completing
in two clock cycles. Figure 12-12 shows a two-clock read and write memory bank. The
required parts include:
(8) 16K*4 SRAMs, 25-ns access time with separate I/O pins
(4) 74F244 buffers
(2) 74F32 OR gates
(1) PAL16L8D (or equivalent)
(1) 74F74 D-type flip-flop
(2) 74F373 transparent latches
(1) 74AS21 AND gate
(1) 74F04 inverter
12-20
MC68030 USER’S MANUAL
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