MC68030 Datasheet, PDF (521/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
clock edge of the MC68030's clock after AS asserts. Four counters are used to provide
enough drive capability to avoid an additional buffer propagation delay. Each counter drives
eight memory devices.
The third section contains the memory devices. The most important feature of the memory
devices used in this design is the separate data-in and data-out pins, which allow the
SRAMs to be constantly enabled before address decode is complete without causing data
bus contention. If the designer wishes to include some type of enable circuitry to take
advantage of low bus utilization, the timing in this design will be preserved if the memory's
E signal is asserted within 13 ns after the falling edge of state S0.
MOTOROLA
MC68030 USER’S MANUAL
12-25