MC68030 Datasheet, PDF (296/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
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Figure 9-5. Example Translation Tree Layout in Memory
9.1.1 Translation Control
The translation control register (TC) defines the size of pages in memory, selects the root
pointer register to be used for supervisor accesses, indicates whether the top level of the
translation tree is indexed by function code, and specifies the number of logical address bits
used to index into the various levels of the translation tree. The initial shift (IS) field of the
TC register defines the size of the logical address space; it contains the number of most
significant address bits that are ignored in the translation table lookup. For example, if the
IS field is set to zero, the logical address space is 2³² bytes. On the other hand, if the IS field
is set to 15, the logical address space contains only 2³²â€”2¹ bytes.
The page size (PS) field of the TC register specifies the page size for the system. The
number of pages in the system is equal to the logical address space divided by the page
size. The maximum number of pages that can be defined by a translation tree is greater than
16 million (2³²/2⁸). The minimum number is 4 (2¹⁷/2¹⁵). The function code can also be used
in the table lookup, defining as many as seven regions of the above size (FC=0-6). The
entire range of the logical address space(s) can be defined by translation tables of many
sizes. The MC68030 provides flexibility that simplifies the implementation of large
translation tables.
The use of a tree structure with as many as five levels of tables provides granularity in
translation table design. The LIMIT field of the root pointer can limit the value of the first
index and limits the actual number of descriptors required. Optionally, the top level of the
structure can be indexed by function code bits. In this case, the pointer table at this level
contains eight descriptors. The next level of the structure (or the top level when the FCL bit
of the TC register is set to zero) is indexed by the most significant bits of the logical address
(disregarding the number of bits specified by the IS field). The number of logical address bits
used for this index is specified by the TIA field of the TC register. If, for example, the TIA
field contains the value 5, the index for this level contains five bits, and the pointer table at
this level contains at most 32 descriptors.
Similarly, the TIB, TIC, and TID fields of the TC register define the indexes for lower levels
of the translation table tree. When one of these fields contains zero, the remaining TIx fields
are ignored; the last nonzero TIx field defines the index into the lowest level of the tree
structure. The tables selected by the index at this level are page tables; every descriptor in
these tables is (or represents) a page descriptor. Figure 9-6 shows how the TIx fields of the
TC register apply to a function code and logical address.
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Figure 9-6. Derivation of Table Index Fields
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MC68030 USER’S MANUAL
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