MC68030 Datasheet, PDF (270/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
When several devices are connected to the same interrupt level, each device should hold
its interrupt priority level constant until its corresponding interrupt acknowledge cycle to
ensure that all requests are processed.
Table 8-4 lists the interrupt levels, the states of IPL2-IPL0 that define each level, and the
mask value that allows an interrupt at each level.
Table 8-4. Interrupt Levels and Mask Values
Requested
Interrupt Level
0*
1
2
3
4
5
6
7
Control Line Status
IP2
High
High
High
High
Low
Low
Low
Low
IP1
High
High
Low
Low
High
High
Low
Low
IP0
High
Low
High
Low
High
Low
High
Low
*Indicates that no interrupt is requested.
Interrupt Mask Level
Required for Recognition
N/A*
0
0-1
0-2
0-3
0-4
0-5
0-7
Priority level 7, the nonmaskable interrupt (NMI), is a special case. Level 7 interrupts cannot
be masked by the interrupt priority mask, and they are transition sensitive. The processor
recognizes an interrupt request each time the external interrupt request level changes from
some lower level to level 7, regardless of the value in the mask. Figure 8-3 shows two
examples of interrupt recognitions, one for level 6 and one for level 7. When the MC68030
processes a level 6 interrupt, the status register mask is automatically updated with a value
of 6 before entering the handler routine so that subsequent level 6 interrupts are masked.
Provided no instruction that lowers the mask value is executed, the external request can be
lowered to level 3 and then raised back to level 6 and a second level 6 interrupt is not
processed. However, if the MC68030 is handling a level 7 interrupt (status register mask set
to 7) and the external request is lowered to level 3 and than raised back to level 7, a second
level 7 interrupt is processed. The second level 7 interrupt is processed because the level 7
interrupt is transition sensitive. A level 7 interrupt is also generated by a level comparison if
the request level and mask level are at seven and the priority mask is then set to a lower
level (with the MOVE to SR or RTE instruction, for example). As shown in Figure 8-3 for level
6 interrupt request level and mask level, this is the case for all interrupt levels.
8-16
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