MC68030 Datasheet, PDF (379/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
The F-line operation word contains the CpID field in bits [9-11] and 001111 in bits [8:3] to
identify the cpTRAPcc instruction. Bits [0-2] of the cpTRAPcc F-line operation word specify
the number of optional operand words in the instruction format. The instruction format can
include zero, one, or two operand words.
The second word of the cpTRAPcc instruction format contains the coprocessor condition
selector in bits [0-5] and should contain zeros in bits [6-15] to maintain compatibility with
future M68000 products. This word is written to the condition CIR of the coprocessor to
initiate execution of the cpTRAPcc instruction by the coprocessor.
If the coprocessor requires additional information to evaluate a condition, the instruction can
include this information in extension words. These extension words follow the word
containing the coprocessor condition selector field in the cpTRAPcc instruction format.
The operand words of the cpTRAPcc F-line operation word follow the coprocessor-defined
extension words. These operand words are not explicitly used by the MC68030, but can be
used to contain information referenced by the cpTRAPcc exception handling routines. The
valid encodings for bits [0-2] of the F-line operation word and the corresponding numbers of
operand words are listed in Table 10-1. Other encodings of these bits are invalid for the
cpTRAPcc instruction.
Table 10-1. cpTRAPcc Opmode
Opmode
010
011
100
Optional Words in
instructional Format
One
Two
Zero
10.2.2.4.2 Protocol. Figure 10-8 shows the protocol for the cpTRAPcc instructions. The
MC68030 transfers the condition selector to the coprocessor by writing the word following
the operation word to the condition CIR. The main processor then reads the response CIR
to determine its next action. The coprocessor can, using a response primitive, request any
services necessary to evaluate the condition. If the coprocessor returns the true condition
indicator, the main processor initiates exception processing for the cpTRAPcc exception
(refer to 10.5.2.4 cpTRAPcc Instruction Traps). If the coprocessor returns the false
condition indicator, the main processor executes the next instruction in the instruction
stream.
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MC68030 USER’S MANUAL
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