MC68030 Datasheet, PDF (339/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
9.7.5 Register Programming Considerations
If the entries in the address translation cache (ATC) are no longer valid when a reset
operation occurs, an explicit flush operation must be specified by the software. The
assertion of RESET disables translations by clearing the E bits of the TC and TTx registers,
but it does not flush the ATC. Flushing of the ATC is optional under control of the FD bit of
the PMOVE instruction that loads a new value into the SRP, CRP, TT0, TT1, or TC register.
The programmer of the MMU must be aware of effects resulting from loading certain
registers. A subsequent section describes these effects. The MMUSR values lend
themselves to the use of a case structure for branching to appropriate routines in a bus error
handler. An example of a flowchart that implements this technique is shown in another
section. A third section describes the conditions that result in MMU exceptions.
9.7.5.1 REGISTER SIDE EFFECTS. The PMOVE instruction is used to load or read any of
the MMU registers (CRP, SRP, TC, MMUSR, TT0, and TT1). Since loading the root
pointers, the translation control register, or the transparent translation registers with new
values can cause some or all of the address translations to change, it may be desired to
flush the ATC of its contents any time these registers are written. The opcodes of the
PMOVE instructions that write to CRP, SRP, TC, TT0, and TT1 contain a flush disable (FD)
bit that optionally flushes the ATC when these instructions are executed. If the FD bit equals
one, the ATC is not flushed when the instruction is executed. If the FD bit equals zero, the
ATC is flushed during the execution of the PMOVE instruction.
9.7.5.2 MMU STATUS REGISTER DECODING. The seven status bits in the MMU status
register (MMUSR) indicate conditions to which the operating system should respond. In a
typical bus error handler routine, the flows shown in Figures 9-39 and 9-40 can be used to
determine the cause of an MMU fault. The PTEST instructions set the bits in the MMUSR
appropriately, and the program can branch to the appropriate code segment for the
condition. Figure 9-39 shows the flow for a PTEST instruction for the ATC (level 0), and
Figure 9-40 shows the flow for a PTEST instruction that accesses an address translation
tree (levels 1-7).
MOTOROLA
MC68030 USER’S MANUAL
9-51